Clocking Blocks in SystemVerilog are used to simplify the process of handling clocked signals and timing within verification environments. They help manage synchronization between different parts of a testbench and ensure that signals are correctly sampled or driven according to specific timing requirements.

Purpose of Clocking Blocks

• Synchronization: Align signals with specific clock edges to ensure proper timing.
• Timing Control: Define how and when signals should be sampled or driven.
• Simplify Testbenches: Make testbenches more readable and maintainable by grouping timing-related code.

Syntax and Structure

A clocking block is defined with the clocking keyword and specifies a clock and timing behavior. It includes:

• Clocking Event: The clock signal that governs the timing for the block.
• Input and Output Variables: Signals that are either sampled or driven within the block.
• Timing Controls: The timing at which signals are sampled or driven relative to the clock.

Syntax:

verilog
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clocking clocking_name @(posedge clk);
    // Input and output variables
    input signal_name;
    output signal_name;
endclocking

Example: Basic Clocking Block

Here’s a simple example of a clocking block:

verilog
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module test;
    reg clk;
    reg rst;
    reg [7:0] data_in;
    wire [7:0] data_out;

    // Clocking block
    clocking cb @(posedge clk);
        input rst;
        input [7:0] data_in;
        output [7:0] data_out;
    endclocking

    initial begin
        clk = 0;
        rst = 1;
        data_in = 8'h00;
        #10 rst = 0;
        #20 data_in = 8'hFF;
    end

    always #5 clk = ~clk;

    // Example of using the clocking block
    always @(posedge clk) begin
        cb.data_out = cb.data_in;
    end
endmodule

In this example:

• The clocking block cb is defined to use the positive edge of clk.
• It includes rst, data_in, and data_out as signals.
• cb.data_out is driven with the value of cb.data_in on each positive clock edge.

Clocking Block Timing Controls

Clocking blocks support several timing controls:

• @: Specifies the clock edge when the signals are sampled or driven.
• input and output: Define how signals are sampled and driven relative to the clock edge.

Example: Timing Control

verilog
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module test;
    reg clk;
    reg [7:0] data;
    reg ready;

    // Clocking block with timing control
    clocking cb @(posedge clk);
        input data;
        output ready;
        // Sample `data` on the positive edge of `clk` and drive `ready` on the next positive edge
    endclocking

    initial begin
        clk = 0;
        data = 8'h00;
        ready = 0;
        #10 data = 8'hFF;
    end

    always #5 clk = ~clk;

    // Example usage
    always @(posedge clk) begin
        cb.ready = (cb.data == 8'hFF);
    end
endmodule

In this example:

• cb.data is sampled on the positive edge of clk.
• cb.ready is driven based on the sampled cb.data value.

Clocking Blocks with Multiple Clocks

Clocking blocks can be used with multiple clocks to handle more complex timing scenarios.

Example: Multiple Clocks

verilog
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module test;
    reg clk1, clk2;
    reg [7:0] data1, data2;
    wire [7:0] result;

    // Clocking block for clk1
    clocking cb1 @(posedge clk1);
        input data1;
        output result;
    endclocking

    // Clocking block for clk2
    clocking cb2 @(posedge clk2);
        input data2;
    endclocking

    initial begin
        clk1 = 0;
        clk2 = 0;
        data1 = 8'h00;
        data2 = 8'hFF;
        #10 data1 = 8'hAA;
        #20 data2 = 8'hBB;
    end

    always #5 clk1 = ~clk1;
    always #7 clk2 = ~clk2;

    // Example of using clocking blocks with multiple clocks
    always @(posedge clk1) begin
        cb1.result = cb1.data1 + cb2.data2; // Using data from different clock domains
    end
endmodule

In this example:

• cb1 is synchronized with clk1, while cb2 is synchronized with clk2.
• Data from different clock domains is used together in the clocking block.