Verilog Classes
Verilog Classes
In SystemVerilog, classes are used to support object-oriented programming (OOP), providing features like encapsulation, inheritance, and polymorphism. Classes are useful for creating modular and reusable code, particularly in testbenches and complex verification tasks.
Basic Class Definition
A class in SystemVerilog is defined using the class keyword. It can contain properties and methods (functions and tasks).
Syntax:
verilogclass class_name; // Data members (properties) data_type property_name; // Constructor function new(); // Initialization code endfunction // Methods (functions and tasks) function void method_name(); // Method code endfunction endclass
Example: Basic Class
Here's a basic example of a class representing a Transaction:
verilogclass Transaction; // Properties bit [7:0] address; bit [15:0] data; // Constructor function new(bit [7:0] addr, bit [15:0] dat); address = addr; data = dat; endfunction // Method function void display(); $display("Address: %h, Data: %h", address, data); endfunction endclass
Creating and Using an Object
To use a class, you create an instance (object) of that class:
verilogmodule test; // Declare a variable of type Transaction Transaction txn; initial begin // Create an instance of the Transaction class txn = new(8'hA0, 16'hBEEF); // Call the display method txn.display(); end endmodule
Inheritance
Classes can inherit from other classes, enabling code reuse and the creation of class hierarchies.
Syntax:
verilogclass base_class; // Base class properties and methods endclass class derived_class extends base_class; // Additional properties and methods endclass
Example: Inheritance
verilogclass BaseTransaction; bit [7:0] address; function new(bit [7:0] addr); address = addr; endfunction function void display(); $display("Address: %h", address); endfunction endclass class AdvancedTransaction extends BaseTransaction; bit [15:0] data; function new(bit [7:0] addr, bit [15:0] dat); super.new(addr); // Call base class constructor data = dat; endfunction function void display(); super.display(); // Call base class method $display("Data: %h", data); endfunction endclass
Polymorphism
Polymorphism allows a base class reference to point to a derived class object.
Example:
verilogmodule test; BaseTransaction base_txn; AdvancedTransaction adv_txn; initial begin // Create instances base_txn = new(8'hA0); adv_txn = new(8'hA1, 16'hBEEF); // Use base class reference to point to derived class object base_txn = adv_txn; base_txn.display(); // Calls AdvancedTransaction's display end endmodule
Virtual Methods
Methods declared as virtual in the base class can be overridden in derived classes.
Example:
verilogclass BaseTransaction; function void display(); $display("BaseTransaction display"); endfunction endclass class DerivedTransaction extends BaseTransaction; function void display(); $display("DerivedTransaction display"); endfunction endclass
Constraints
Constraints define conditions on property values, often used for random generation in verification.
Example:
verilogclass RandomTransaction; randc bit [7:0] address; randc bit [15:0] data; constraint addr_c { address >= 8'h00 && address <= 8'hFF; } constraint data_c { data >= 16'h0000 && data <= 16'hFFFF; } endclass
Class Inheritance and Polymorphism
Classes support inheritance and polymorphism, allowing derived classes to extend base classes and enabling objects of different classes to be handled through a common interface.