IceStudio - Basic Digital Clock

Creating a Basic Digital Clock using IceStudio involves designing a system that counts seconds, minutes, and hours and displays them on 7-segment displays. This project will cover all steps from setup to implementation, including the design and code. Here’s a detailed walkthrough:

1. Setup IceStudio

Download and Install IceStudio:
- Visit the IceStudio GitHub page or the official website.
- Download the installer for your operating system (Windows, macOS, or Linux) and follow the installation instructions.
Connect Your FPGA Board:
- Connect your FPGA development board (e.g., Lattice iCE40) to your computer via USB.
Open IceStudio:
- Launch IceStudio from your desktop or applications folder.

2. Create a New Project

Start a New Design:
- Open IceStudio and select “File” > “New” to start a new project.
Set Up Project Parameters:
- Choose the FPGA device that matches your development board (e.g., iCE40-HX8K).
- Save the project with a name like “BasicDigitalClock”.

3. Design the Digital Clock Logic

1. Add a Clock Source

Drag a Clock Block:
- From the components library, drag a Clock block to the canvas.
- Configure the clock frequency to match your FPGA board’s clock (e.g., 12 MHz).

2. Create Counters for Seconds, Minutes, and Hours

Seconds Counter:
- Drag a Counter block to the canvas.
- Configure it to count seconds. Set the maximum count value to represent 60 (for 60 seconds).
- Connect the clock output to the counter’s clock input.
Minutes Counter:
- Drag another Counter block for minutes.
- Configure it to count up every 60 seconds. Set the maximum count value to 60.
- Connect the seconds counter’s overflow output to the minutes counter’s clock input.
Hours Counter:
- Drag a third Counter block for hours.
- Configure it to count up every 60 minutes. Set the maximum count value to 24 (for a 24-hour format) or 12 (for a 12-hour format).
- Connect the minutes counter’s overflow output to the hours counter’s clock input.

3. Add 7-Segment Displays

Drag 7-Segment Display Blocks:
- Drag 7-Segment Display blocks from the library for hours, minutes, and seconds.
Connect Counters to Displays:
- Connect the output of the seconds counter to the 7-segment display for seconds.
- Connect the output of the minutes counter to the 7-segment display for minutes.
- Connect the output of the hours counter to the 7-segment display for hours.
Configure the 7-Segment Displays:
- Ensure that each display is configured to show the values from its respective counter correctly.

4. Configure Pin Mapping

Assign FPGA Pins:
- Go to the Pin Configuration section in IceStudio.
- Map the outputs of the 7-segment displays to the correct physical pins on your FPGA board.
- Assign pins for each segment of the 7-segment displays (e.g., A, B, C, D, E, F, G, and DP).
Create a Pin Constraint File (if needed):
- You may need to manually create or modify a pin constraint file to specify exact pin locations on your FPGA board.

4. Generate and Synthesize the Design

Run Synthesis:
- Click on the Synthesize button in IceStudio. This converts your graphical design into a netlist for the FPGA.
Place and Route:
- IceStudio will automatically handle the placement and routing of your design.
Generate Bitstream:
- Click on Generate Bitstream to create the bitstream file required to program your FPGA.

5. Program the FPGA

Connect Programmer Tool:
- Ensure that your FPGA board is connected to your computer.
Load the Bitstream:
- Use the iceprog tool or the integrated programming feature in IceStudio to upload the bitstream to your FPGA.
Verify the Digital Clock:
- Once programmed, your FPGA should display the current time on the 7-segment displays, with the clock ticking in seconds, minutes, and hours.

6. Example Code

Here’s a simplified example of Verilog code for the digital clock counters:

Seconds Counter

verilog
module SecondsCounter (
    input clk,          // System clock
    input rst,          // Reset
    output reg [5:0] seconds, // Seconds output
    output reg carry    // Carry out to minutes counter
);

    reg [25:0] count;
    parameter MAX_COUNT = 1000000; // Adjust this value based on your clock frequency

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            count <= 0;
            seconds <= 0;
            carry <= 0;
        end else begin
            if (count < MAX_COUNT-1) begin
                count <= count + 1;
            end else begin
                count <= 0;
                if (seconds < 59) begin
                    seconds <= seconds + 1;
                end else begin
                    seconds <= 0;
                    carry <= 1;
                end
            end
        end
    end
endmodule

Minutes Counter

verilog
module MinutesCounter (
    input clk,          // System clock
    input rst,          // Reset
    input carry_in,     // Carry from seconds counter
    output reg [5:0] minutes, // Minutes output
    output reg carry    // Carry out to hours counter
);

    reg [25:0] count;
    parameter MAX_COUNT = 1000000; // Adjust this value based on your clock frequency

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            count <= 0;
            minutes <= 0;
            carry <= 0;
        end else begin
            if (count < MAX_COUNT-1) begin
                count <= count + 1;
            end else begin
                count <= 0;
                if (carry_in) begin
                    if (minutes < 59) begin
                        minutes <= minutes + 1;
                        carry <= 0;
                    end else begin
                        minutes <= 0;
                        carry <= 1;
                    end
                end
            end
        end
    end
endmodule

Hours Counter

verilog
module HoursCounter (
    input clk,          // System clock
    input rst,          // Reset
    input carry_in,     // Carry from minutes counter
    output reg [4:0] hours // Hours output
);

    reg [25:0] count;
    parameter MAX_COUNT = 1000000; // Adjust this value based on your clock frequency

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            count <= 0;
            hours <= 0;
        end else begin
            if (count < MAX_COUNT-1) begin
                count <= count + 1;
            end else begin
                count <= 0;
                if (carry_in) begin
                    if (hours < 23) begin
                        hours <= hours + 1;
                    end else begin
                        hours <= 0;
                    end
                end
            end
        end
    end
endmodule

7. Save and Document Your Work

Save the Project: Save your IceStudio project and any associated files.
Document Configuration: Note down the pin assignments, clock settings, and any other relevant details for future reference.

Summary

This detailed walkthrough covers creating a basic digital clock using IceStudio. It involves setting up counters for seconds, minutes, and hours, connecting them to 7-segment displays, and configuring the FPGA pins. The provided Verilog code examples demonstrate how to implement the counters.

For visual aids and additional context, refer to IceStudio’s documentation or community tutorials that may include screenshots and further examples.

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